Packaging structure for gallium nitride devices
US11107753B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2018 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Jan 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implementations of semiconductor packages may include: a substrate having one or more traces on a first side and one or more traces on a second side of the substrate. The substrate may be rigid. The packages may include at least one die mechanically and electrically coupled to the first side of the substrate. The die may be a high voltage die. The package may include one or more traces along one or more edges of the substrate. The one or more traces along the one or more edges of the substrate provide electrical connectivity between the one or more traces on the first side of the substrate and the one or more traces on the second side of the substrate. The package may also include a molding compound encapsulating at least the first and the one or more edges of the ceramic substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.