Inventor · Scottsdale, AZ, US

Stephen St. Germain

55Patents
7h-index
37Co-inventors
72Inventor score

Filing activity: Sep 17, 1997 → Mar 5, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6889429B2 Method of making a lead-free integrated circuit package Emerging Cross-Sectional Technologies 24 Expired
US7319266B2 Encapsulated electronic device structure Electricity 22 Expired
US6677672B2 Structure and method of forming a multiple leadframe semiconductor device Electricity 20 Expired
US6713317B2 Semiconductor device and laminated leadframe package Electricity 19 Expired
US6103548A Semiconductor device and method of manufacture Electricity 13 Expired
US7298034B2 Multi-chip semiconductor connector assemblies Electricity 10 Expired
US6833290B2 Structure and method of forming a multiple leadframe semiconductor device Electricity 8 Expired
US7495323B2 Semiconductor package structure having multiple heat dissipation paths and method of manufacture Electricity 7 Active
US6747341B2 Integrated circuit and laminated leadframe package Electricity 7 Expired
US7202105B2 Multi-chip semiconductor connector assembly method Electricity 5 Expired
US11955412B2 Low stress asymmetric dual side module Electricity 4 Active
US10090199B2 Semiconductor device and method for supporting ultra-thin semiconductor die Electricity 4 Active
US11462515B2 Low stress asymmetric dual side module Electricity 4 Active
US11908840B2 Low stress asymmetric dual side module Electricity 4 Active
US11948870B2 Low stress asymmetric dual side module Electricity 4 Active
US11469163B2 Low stress asymmetric dual side module Electricity 4 Active
US11894347B2 Low stress asymmetric dual side module Electricity 4 Active
US7135761B2 Robust power semiconductor package Electricity 3 Expired
US7202106B2 Multi-chip semiconductor connector and method Electricity 2 Expired
US7180170B2 Lead-free integrated circuit package structure Emerging Cross-Sectional Technologies 1 Expired
US7476959B2 Encapsulated electronic device Electricity 1 Active
US7935575B2 Method of forming a semiconductor package and structure therefor Electricity 1 Active
US7397120B2 Semiconductor package structure for vertical mount and method Electricity 1 Expired
US7875964B2 Multi-chip semiconductor connector and method Electricity 1 Active
US9911684B1 Holes and dimples to control solder flow Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.