Inner spacer formation in multi-gate transistors
US11107904B2 · kind B2 · utility
0Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Oct 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02332
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes forming a structure including multiple nanowires vertically stacked above a substrate; depositing a dielectric material layer wrapping around the nanowires; performing a treatment process to a surface portion of the dielectric material layer; selectively etching the surface portion of the dielectric material layer; repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed; and forming a gate structure engaging the nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.