Techniques for reducing tip to tip shorting and critical dimension variation during nanoscale patterning
US11114299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.