IC die with dummy structures

US11114344B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Hui-Wen Lin · Jianshi, TW
• Nui Chong · San Jose, US
• Myongseob Kim · Pleasanton, US
• Henley Liu · San Jose, US
• Ping-Chin Yeh · San Jose, US
• Cheang-Whang Chang · Mountain View, US

Key dates

• Filing date: Feb 28, 2020
• Grant date: Sep 7, 2021
• Expiry date: Feb 28, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.