Integrated circuitry, memory integrated circuitry, and methods used in forming integrated circuitry
US11114379B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2018 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Sep 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method used in forming integrated circuitry comprises forming a stack of vertically-alternating tiers of different composition materials. A stair-step structure is formed into the stack and an upper landing is formed adjacent and above the stair-step structure. The stair-step structure is formed to comprise vertically-alternating tiers of the different composition materials. A plurality of stairs individually comprise two of the tiers of different composition materials. At least some of the stairs individually have only two tiers that are each only of a different one of the different composition materials. An upper of the stairs that is below the upper landing comprises at least four of the tiers of different composition materials. Structure independent of method is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.