Multi-division 3D NAND memory device
US11114439B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 27, 2020 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Aug 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for forming a staircase structure of 3D memory. The method includes providing a substrate, forming an alternating layer stack over the substrate, forming a plurality of block regions over a surface of the alternating layer stack, forming a first plurality of staircase structures to expose a portion of a first number of top-most layer stacks at each of the block regions and removing the first number of the layer stacks at a second plurality of staircase structures at each of the block regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.