Gate-all-around field-effect transistor device
US11114529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Aug 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.