Semiconductor device having multiple dimensions of gate structures and method for fabricating the same
US11114536B1 · kind B1 · utility
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19Claims
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Key dates
| Filing date | Feb 26, 2020 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Feb 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
Abstract
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area adjacent to the array area, a first gate structure positioned in the array area, and a second gate structure positioned in the peripheral area. A width of the first gate structure is less than a width of the second gate structure, and a depth of the first gate structure is less than a depth of the second gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.