Three-dimensional memory device and manufacturing method thereof
US11121152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2019 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Jan 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. An opening is formed penetrating the alternating dielectric stack in a thickness direction of the substrate. A blocking layer is formed on a sidewall of the opening. A trapping layer is formed in the opening, and the trapping layer is formed on the blocking layer. The trapping layer includes a lower portion and an upper portion disposed above the lower portion. A thickness of the upper portion in a horizontal direction is greater than a thickness of the lower portion in the horizontal direction. The thickness distribution of the trapping layer is modified for improving the electrical performance of the 3D memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.