Integrated trench capacitor with top plate having reduced voids
US11121207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2016 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Mar 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.