Low resistance crosspoint architecture
US11121317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2019 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Nov 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8825
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.