Physically aware topology synthesis of a network
US11121933B2 · kind B2 · utility
19Cited by
1References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 27, 2019 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Dec 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
System and methods are disclosed for synthesis of network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting output includes placement of the elements on a floorplan of a chip that represents the network, such as the NoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.