Planarization of semiconductor packages and structures resulting therefrom
US11127644B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2019 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Sep 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.