Dynamic P2L asynchronous power loss mitigation
US11132044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Aug 23, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.