Interconnect systems and methods using memory links to send packetized data between different data handling devices of different memory domains
US11132127B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2018 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Oct 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.