Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
US11138050B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Mar 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.