Memory device with temporary kickdown of source voltage before sensing
US11139018B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Aug 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are controlled to reduce the channel resistance. Vcelsrc can be temporarily reduced, e.g., provided with a negative voltage kick, while Vp-well is non-decreasing during a read operation. The negative voltage kick decreases a body bias of the NAND string in its channel to reduce the channel resistance and increase the current. The negative voltage kick can be initiated when a bit line clamp transistor is made conductive to allow a current to flow in the NAND string. The magnitude and duration of the negative voltage kick can be adjusted based on various factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.