Neighbor word line compensation full sequence program scheme
US11139031B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Jun 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to determine data states for a first set of memory cells of a neighboring word line of the set of word lines, determine a bit line voltage bias and a sense time for a memory cell of a second set of memory cells of the selected word line based on a data state determined for a memory cell for each memory cell of the second set of memory cells, and perform a verify operation on the selected word line using the bit line voltage bias and the sense time determined for each memory cell of the second set of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.