Neighboring or logical minus word line dependent verify with sense time in programming of non-volatile memory
US11139038B1 · kind B1 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Jun 17, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Jun 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprising performing a read operation of one or more memory cells neighboring a target memory cell, thereby determining a data pattern of the one or more neighboring memory cells, storing the data pattern and, during a program operation of the target memory cell, adjusting a verify voltage level according to the stored data pattern of the one or more neighboring memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.