3D circuit provided with mesa isolation for the ground plane zone
US11139209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Dec 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/022
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A production of a device with superimposed levels of components including in this order providing on a given level N1 provided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N2, above said given level N1, the stack including a ground plane layer situated between the first and second semiconductor layers as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer. A gate is formed on at least one island. Distinct portions are etched in the second semiconductor ground plane layer. An isolation zone is formed around the island by the gate and the island.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.