Semiconductor package structure and method for manufacturing the same
US11139282B2 · kind B2 · utility
2Cited by
13References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 26, 2018 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Jul 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.