Write leveling a memory device
US11144241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Aug 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.