Retire queue compression
US11144324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Sep 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.