Non-volatile memory with a well bias generation circuit
US11145382B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | May 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A leakage measuring circuit includes a bias input node control circuit and provides a signal indicative of a leakage current through the bias input node. The bias input node control circuit includes a first input to receive an indication of a reference voltage, a second input to receive an indication of a voltage of the bias input node, and an output to bias the bias input node at the reference voltage based on a relationship between the first and second input. A well voltage bias circuit provides a well bias voltage and includes a well bias control circuit including a first input to receive the signal indicative of the leakage current, a second input to receive a signal indicative of a reference leakage current value, and an output for controlling the well bias voltage based on a relationship between the first and second input of the well bias control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.