Method for forming and patterning a layer and/or substrate
US11145509B2 · kind B2 · utility
1Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Apr 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76831
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.