Field-effect transistors with dual thickness gate dielectrics

US11145732B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ayan Kar · Portland, US
• Kalyan C. Kolluru · Portland, US
• Nicholas A. Thomson · Hillsboro, US
• Mark Armstrong · Portland, US
• Sameer Jayanta Joglekar · Hillsboro, US
• Rui Ma · Naperville, US
• Sayan Saha · Portland, US
• Hyuk-Ju Ryu · Hillsboro, US
• Akm A. Ahsan · Portland, US

Key dates

• Filing date: Nov 30, 2019
• Grant date: Oct 12, 2021
• Expiry date: Jan 8, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/307

Abstract

Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.