Method of manufacturing a semiconductor device
US11145733B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Sep 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.