Semiconductor layer between source/drain regions and gate spacers

US11152461B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Rishabh Mehandru · Portland, US
• Anupama Bowonder · Portland, US
• Biswajeet Guha · Hillsboro, US
• Tahir Ghani · Portland, US
• Stephen M. Cea · Hillsboro, US
• William Hsu · Hillsboro, US
• Szuya S. Liao · Portland, US
• Pratik A. Patel · Berkeley, US

Key dates

• Filing date: May 18, 2018
• Grant date: Oct 19, 2021
• Expiry date: Feb 18, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.