William Hsu
46Patents
5h-index
60Co-inventors
72Inventor score
Filing activity: Oct 14, 1976 → Mar 29, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6250584A | Missile fin locking mechanism | Mechanical Engineering; Lighting; Heating | 18 | Expired |
| US6352217B1 | Missile fin locking and unlocking mechanism including a mechanical force amplifier | Mechanical Engineering; Lighting; Heating | 14 | Expired |
| US4518004A | Multifunction valve | Emerging Cross-Sectional Technologies | 11 | Expired |
| US4526058A | Centering and lock mechanism for hydraulic actuator | Emerging Cross-Sectional Technologies | 8 | Expired |
| US11233152B2 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Electricity | 5 | Active |
| US7195197B2 | Techniques for controlling a fin with unlimited adjustment and no backlash | Mechanical Engineering; Lighting; Heating | 5 | Expired |
| US11855223B2 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Electricity | 5 | Active |
| US11342411B2 | Cavity spacer for nanowire transistors | Electricity | 4 | Active |
| US4232699A | Hydro-mechanical failure detection and latching apparatus | Emerging Cross-Sectional Technologies | 3 | Expired |
| US11908856B2 | Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact | Performing Operations; Transporting | 2 | Active |
| US11302790B2 | Fin shaping using templates and integrated circuit structures resulting therefrom | Electricity | 2 | Active |
| US11404578B2 | Dielectric isolation layer between a nanowire transistor and a substrate | Electricity | 2 | Active |
| US4180243A | Automatic and manual linear reversion control mechanism | Emerging Cross-Sectional Technologies | 2 | Expired |
| US11824116B2 | Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact | Electricity | 2 | Active |
| US11799009B2 | Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact | Electricity | 2 | Active |
| US11894368B2 | Gate-all-around integrated circuit structures fabricated using alternate etch selective material | Electricity | 1 | Active |
| US11929396B2 | Cavity spacer for nanowire transistors | Electricity | 1 | Active |
| US11869891B2 | Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process | Electricity | 1 | Active |
| US12294006B2 | Gate-all-around integrated circuit structures having insulator substrate | Electricity | 0 | Active |
| US12328905B2 | Cavity spacer for nanowire transistors | Electricity | 0 | Active |
| US11152461B2 | Semiconductor layer between source/drain regions and gate spacers | Electricity | 0 | Active |
| US12068314B2 | Fabrication of gate-all-around integrated circuit structures having adjacent island structures | Electricity | 0 | Active |
| US11705518B2 | Isolation schemes for gate-all-around transistor devices | Electricity | 0 | Active |
| US11495672B2 | Increased transistor source/drain contact area using sacrificial source/drain layer | Electricity | 0 | Active |
| US12288789B2 | Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact | Performing Operations; Transporting | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.