Memory device and erasing and verification method thereof
US11158380B1 · kind B1 · utility
0Cited by
8References
16Claims
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Key dates
| Filing date | Jun 18, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, and a P-well. The control circuit performs an erasing and verification method, wherein the erasing and verification method includes erasing the selected memory block during an erasing stage; and maintaining the bottom select gate to be turned on during a maintaining period before the top select gate are turned on during a verification stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.