Apparatus and methods for configurable bit line isolation in non-volatile memory
US11158384B1 · kind B1 · utility
3Cited by
1References
20Claims
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Key dates
| Filing date | May 20, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | May 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a plurality of NAND strings having a common set of word lines. Each NAND string includes data memory cells for data storage and dummy memory cells connected in series with the data memory cells. A first group of NAND strings includes dummy memory cells with a first pattern of threshold voltages and a second group of NAND strings includes dummy memory cells with a second pattern of threshold voltages for separate isolation of data memory cells of the first and second groups of NAND strings from corresponding bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.