Method, control system and plant for processing a semiconductor wafer, and semiconductor wafer

US11158549B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Stefan WELSCH · Polling, DE
• Christof Weber · Burghausen, DE
• Axel Beyer · Munich, DE

Key dates

• Filing date: Jun 5, 2018
• Grant date: Oct 26, 2021
• Expiry date: Aug 24, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/12
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Semiconductor wafers, are processed using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.