Parasitic capacitance reduction in GaN-on-silicon devices
US11158575B2 · kind B2 · utility
2Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2018 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Jun 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.