Systems and methods for evaluating critical dimensions based on diffraction-based overlay metrology
US11162907B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Dec 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for evaluating critical dimensions of a semiconductor device are provided. An exemplary system includes at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, cause the at least one processor to perform operations. The operations include receiving information of a first set of overlay markings on a first layer of the semiconductor device and information of a second set of overlay markings on a second layer of the semiconductor device. The first layer is lower than the second layer. The operations also include receiving a plurality of diffraction parameters measured from corresponding overlay markings on the first and second layers. The operations further include determining a variation of the critical dimensions on the second layer based on the plurality of diffraction parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.