Warpage reduction
US11164749B1 · kind B1 · utility
1Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Sep 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06548
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Examples described herein provide a method for reducing warpage when stacking semiconductor substrates. In an example, a first substrate is bonded with a second substrate to form a stack. The first substrate comprises a first semiconductor substrate, and the second substrate comprises a second semiconductor substrate. The second semiconductor substrate is thinned, and a first trench is etched into a backside of the thinned second semiconductor substrate. A first stressed material is deposited into the first trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.