Self-aligned double patterning with spatial atomic layer deposition
US11164753B2 · kind B2 · utility
1Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2015 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Feb 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68771
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are self-aligned double patterning methods including feature trimming. The SADP process is performed in a single batch processing chamber in which the substrate is laterally moved between sections of the processing chamber separated by gas curtains so that each section independently has a process condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.