Patent · US Active

Bottom barrier free interconnects without voids

US11164815B2 · kind B2 · utility

0Cited by
19References
15Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 28, 2019
Grant dateNov 2, 2021
Priority date
Expiry dateSep 28, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L23/5283
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Techniques to enable bottom barrier free interconnects without voids. In one aspect, a method of forming interconnects includes: forming metal lines embedded in a dielectric; depositing a sacrificial dielectric over the metal lines; patterning vias and trenches in the sacrificial dielectric down to the metal lines, with the trenches positioned over the vias; lining the vias and trenches with a barrier layer; depositing a conductor into the vias and trenches over the barrier layer to form the interconnects; forming a selective capping layer on the interconnects; removing the sacrificial dielectric in its entirety; and depositing an interlayer dielectric (ILD) to replace the sacrificial dielectric. An interconnect structure is also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.