Semiconductor package and manufacturing method thereof
US11164819B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | May 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1094
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first wafer, a second wafer, and an interconnect. The first wafer includes a first die, a first encapsulating material encapsulating the first die, and a first redistribution structure disposed over the first die and the first encapsulating material. The second wafer includes a second die, a second encapsulating material encapsulating the second die, and a second redistribution structure disposed over the second die and the second encapsulating material, wherein the second redistribution structure faces the first redistribution structure. The interconnect is disposed between the first wafer and the second wafer and electrically connecting the first redistribution structure and the second redistribution structure, wherein the interconnect includes a substrate and a plurality of through vias extending through the substrate for connecting the first redistribution structure and the second redistribution structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.