Contact field plate
US11164970B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Jul 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure disposed over a substrate between a source region and a drain region. A first inter-level dielectric (ILD) layer is disposed over the substrate and the gate structure and a second ILD layer is disposed over the first ILD layer. A field plate etch stop structure is between the first ILD layer and the second ILD layer. A field plate extends from an uppermost surface of the second ILD layer to the field plate etch stop structure. A plurality of conductive contacts extend from the uppermost surface of the second ILD layer to the source region and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.