Controlling NAND operation latency
US11169917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jan 14, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.