Inventor · San Marco Evangelista, IT

Massimo Iaculo

49Patents
4h-index
44Co-inventors
59Inventor score

Filing activity: Feb 19, 2008 → Jun 21, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US8806293B2 Controller to execute error correcting code algorithms and manage NAND memories Emerging Cross-Sectional Technologies 14 Active
US9213603B2 Controller to manage NAND memories Emerging Cross-Sectional Technologies 9 Active
US7603593B2 Method for managing bad memory blocks in a nonvolatile-memory device, and nonvolatile-memory device implementing the management method Physics 8 Active
US11635894B2 Clustered parity for NAND data placement schema Physics 4 Active
US8296508B1 Secure memory device erase Physics 4 Active
US11269545B2 NAND logical-to-physical table region tracking Physics 4 Active
US11521690B2 NAND data placement schema Physics 4 Active
US9189390B2 Wear leveling for erasable memories Physics 3 Active
US10983918B2 Hybrid logical to physical caching scheme Physics 3 Active
US8694718B2 Wear leveling for erasable memories Physics 2 Active
US11269708B2 Real-time trigger to dump an error log Physics 2 Active
US11675709B2 Reading sequential data from memory using a pivot table Emerging Cross-Sectional Technologies 2 Active
US11100996B2 Log data storage for flash memory Physics 2 Active
US10552316B2 Controlling NAND operation latency Emerging Cross-Sectional Technologies 2 Active
US10754580B2 Virtual partition management in a memory device Physics 2 Active
US11474865B2 Allocation schema for a scalable memory area Physics 1 Active
US11106521B2 Fatal error logging in a memory device Physics 1 Active
US11455245B2 Scheme to improve efficiency of garbage collection in cached flash translation layer Physics 1 Active
US11169917B2 Controlling NAND operation latency Emerging Cross-Sectional Technologies 1 Active
US9208901B2 Memory buffer having accessible information after a program-fail Physics 1 Active
US9569129B2 Controller to manage NAND memories Emerging Cross-Sectional Technologies 1 Active
US8880778B2 Memory buffer having accessible information after a program-fail Physics 1 Active
US11955189B2 NAND data placement schema Physics 1 Active
US9183135B2 Preparation of memory device for access using memory access type indicator signal Physics 1 Active
US9971536B2 Controller to manage NAND memories Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.