Cache operations in a hybrid dual in-line memory module
US11169920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2019 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Sep 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.