Checking wafer-level integrated designs for rule compliance
US11170151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Apr 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified to bring non-compliant periphery chip regions into compliance, in response to the determination that the portion of the first chip layout inside the tile area fails to comply with the one or more design rules. A multi-chip wafer is fabricated that includes the chip layouts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.