Polysilicon liners

US11170990B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Krishna Nittala · Sunnyvale, US
• Rui Cheng · San Jose, US
• Karthik Janakiraman · San Jose, US
• Praket P. Jha · San Jose, US
• Jinrui GUO · Santa Clara, US
• Jingmei Liang · San Jose, US

Key dates

• Filing date: Feb 19, 2020
• Grant date: Nov 9, 2021
• Expiry date: Feb 19, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02667
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Aspects of the disclosure provide a method including depositing an underlayer comprising silicon oxide over a substrate, depositing a polysilicon liner on the underlayer, and depositing an amorphous silicon layer on the polysilicon liner. Aspects of the disclosure provide a device intermediate including a substrate, an underlayer comprising silicon oxide formed over the substrate, a polysilicon liner disposed on the underlayer, and an amorphous silicon layer disposed on the polysilicon liner.