Atomic layer deposition and etch for reducing roughness

US11170997B2 · kind B2 · utility

Assignee

• Lam Research Corporation · US

Inventors

• Xiang Zhou · Santa Clara, US
• Naveed Ansari · Fremont, US
• Yoshie Kimura · Castro Valley, US
• Si Yi Li · Fremont, US
• Kazi Sultana · Fremont, US
• Radhika Mani · Fremont, US
• Duming Zhang · Union City, US
• Haseeb Kazi · Santa Clara, US
• Chen Xu · New Providence, US
• Mitchell Brooks · Capitola, US
• Ganesh Upadhyaya · Pleasanton, US

Key dates

• Filing date: Apr 10, 2020
• Grant date: Nov 9, 2021
• Expiry date: Apr 10, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76885
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.