Prioritization of error control operations at a memory sub-system
US11175979B2 · kind B2 · utility
4Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2019 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Oct 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.