Method and system for emulation clock tree reduction
US11176293B1 · kind B1 · utility
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18References
28Claims
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Key dates
| Filing date | Mar 7, 2019 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Mar 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.