Method and system for pattern configuration
US11176307B2 · kind B2 · utility
4Cited by
10References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Nov 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method including: obtaining a device design pattern layout having a plurality of design pattern polygons; automatically identifying, by a computer, a unit cell of polygons in the device design pattern layout; identifying a plurality of occurrences of the unit cell within the device design pattern layout to build a hierarchy; and performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.