Programming memory cells using encoded TLC-fine
US11177002B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Jun 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to receive a parity bit that has been stored using a data structure, and to receive a first subset of host data that includes block data relating to a set of memory cells. The control circuitry may be configured to perform a read operation to identify a second subset of host data that includes additional block data relating to the set of memory cells. The control circuitry may be configured to decode the second subset of host data using the parity bit. The control circuitry may be configured to perform a write operation to write the block data to at least one or more memory cells that are part of the set of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.